\doxysection{FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_f_d_c_a_n___clock_calibration_unit___type_def}{}\label{struct_f_d_c_a_n___clock_calibration_unit___type_def}\index{FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}}


FD Controller Area Network.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_d_c_a_n___clock_calibration_unit___type_def_a021f11746827889db4d06624fb64b014}{CREL}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_d_c_a_n___clock_calibration_unit___type_def_ac0f99874e288f8e874bc8c6f04383d11}{CCFG}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_d_c_a_n___clock_calibration_unit___type_def_afba765bf8f1f8cd8a985ed2599f7c6a9}{CSTAT}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_d_c_a_n___clock_calibration_unit___type_def_abdcb38854d7681894986242209b13b19}{CWD}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_d_c_a_n___clock_calibration_unit___type_def_aa1aafb3ac01b12a57e8e6da1944ee104}{IR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_d_c_a_n___clock_calibration_unit___type_def_a4f06c50c964719ceeb3fa7425c3a2ecb}{IE}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
FD Controller Area Network. 

\label{doc-variable-members}
\Hypertarget{struct_f_d_c_a_n___clock_calibration_unit___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_f_d_c_a_n___clock_calibration_unit___type_def_ac0f99874e288f8e874bc8c6f04383d11}\index{FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}!CCFG@{CCFG}}
\index{CCFG@{CCFG}!FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCFG}{CCFG}}
{\footnotesize\ttfamily \label{struct_f_d_c_a_n___clock_calibration_unit___type_def_ac0f99874e288f8e874bc8c6f04383d11} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def\+::\+CCFG}

Calibration Configuration register, Address offset\+: 0x04 \Hypertarget{struct_f_d_c_a_n___clock_calibration_unit___type_def_a021f11746827889db4d06624fb64b014}\index{FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}!CREL@{CREL}}
\index{CREL@{CREL}!FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CREL}{CREL}}
{\footnotesize\ttfamily \label{struct_f_d_c_a_n___clock_calibration_unit___type_def_a021f11746827889db4d06624fb64b014} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def\+::\+CREL}

Clock Calibration Unit Core Release register, Address offset\+: 0x00 \Hypertarget{struct_f_d_c_a_n___clock_calibration_unit___type_def_afba765bf8f1f8cd8a985ed2599f7c6a9}\index{FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}!CSTAT@{CSTAT}}
\index{CSTAT@{CSTAT}!FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSTAT}{CSTAT}}
{\footnotesize\ttfamily \label{struct_f_d_c_a_n___clock_calibration_unit___type_def_afba765bf8f1f8cd8a985ed2599f7c6a9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def\+::\+CSTAT}

Calibration Status register, Address offset\+: 0x08 \Hypertarget{struct_f_d_c_a_n___clock_calibration_unit___type_def_abdcb38854d7681894986242209b13b19}\index{FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}!CWD@{CWD}}
\index{CWD@{CWD}!FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CWD}{CWD}}
{\footnotesize\ttfamily \label{struct_f_d_c_a_n___clock_calibration_unit___type_def_abdcb38854d7681894986242209b13b19} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def\+::\+CWD}

Calibration Watchdog register, Address offset\+: 0x0C \Hypertarget{struct_f_d_c_a_n___clock_calibration_unit___type_def_a4f06c50c964719ceeb3fa7425c3a2ecb}\index{FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}!IE@{IE}}
\index{IE@{IE}!FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IE}{IE}}
{\footnotesize\ttfamily \label{struct_f_d_c_a_n___clock_calibration_unit___type_def_a4f06c50c964719ceeb3fa7425c3a2ecb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def\+::\+IE}

CCU Interrupt Enable register, Address offset\+: 0x14 \Hypertarget{struct_f_d_c_a_n___clock_calibration_unit___type_def_aa1aafb3ac01b12a57e8e6da1944ee104}\index{FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}!IR@{IR}}
\index{IR@{IR}!FDCAN\_ClockCalibrationUnit\_TypeDef@{FDCAN\_ClockCalibrationUnit\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IR}{IR}}
{\footnotesize\ttfamily \label{struct_f_d_c_a_n___clock_calibration_unit___type_def_aa1aafb3ac01b12a57e8e6da1944ee104} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FDCAN\+\_\+\+Clock\+Calibration\+Unit\+\_\+\+Type\+Def\+::\+IR}

CCU Interrupt register, Address offset\+: 0x10 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
